Content addressable memory (CAM) device enjoy wide use in a variety of applications, including high speed switches and routers for communications. CAM devices can include both binary CAMs and ternary CAMs. Binary CAM devices can include bit locations for accommodating two stored states for comparison: “0” or “1”. Ternary CAM (TCAM) devices can include bit locations for accommodating three states for comparison: “0”, “1”, or “X” (where X is a don't care term, that provides a match regardless of the compare data value).
One example of a CAM device that can reduce current consumption is shown in U.S. Pat. No. 6,515,884, titled CONTENT ADDRESSABLE MEMORY HAVING REDUCED CURRENT CONSUMPTION, issued to Stefan P. Sywyk et al., on Feb. 4, 2003 (Sywyk et al.). Sywyk et al. shows a various particular examples of a CAM device that can include a “pseudo-VSS” arrangement that can conserve power by regulating match line discharge paths.
Another example of a conventional TCAM device is set forth in FIG. 7, and designated by the general reference character 700. A conventional TCAM approach 700 shows one TCAM memory element (cell) which includes two standard six transistor (6-T) type static random access memory (SRAM) cells 702-0 and 702-1 and an exclusive OR (XOR) type compare stack 704.
The 6-T SRAM cells (702-0 and 702-1) can serve as memory elements that establish a comparison state. As shown in FIG. 7, each 6-T SRAM cell (702-0 and 702-1) receives a corresponding bit line pair (706-0 and 706-1), each including one bit line (BL) and one bit line bar (BLB) or “complement”.
The bit line pairs (706-0 and 706-1) per memory element are used for both read and write operations to each SRAM cell (702-0 and 702-1).
An XOR type comparison stack 704 can generate a compare result for the conventional TCAM cell 700. In particular, data values (shown as X and Y) stored in SRAM cells (702-0 and 702-1) can be compared against complementary compare data values (CD and CDB) provided by differential compare data lines (not shown). In the particular arrangement of FIG. 7, in the event of a match compare result, a match line 708 can remain essentially isolated from a low power supply voltage VSS. In the event of a mis-match compare result, an XOR type comparison stack 704 can provide a discharge path to a low power supply voltage VSS.
FIG. 8 represents a layout arrangement of a TCAM cell 800, like that shown in FIG. 7. As shown in FIG. 8, use of bit lines (BL) and bit line bars (BLB) can require two metal resources per SRAM cell 804-0 and 804-1. These metal lines run in the same direction as the compare data lines CD and CDB. As a result, a pitch for compare data lines (CD and CDB) is limited in order to accommodate bit line pairs in the same direction.
An alternate conventional approach can include a single word line for accessing memory elements via bit lines. However, such a conventional approach applies one voltage in a read operation, and another higher voltage in a write operation, in order to maintain read stability and write margins.
A drawback of the above alternate conventional approach can be increased design risk and complexity resulting from the application of different word line voltages for read and write operations.
In light of the above, it would be desirable to arrive at some way of providing a TCAM cell with two data storage cells that can have less design risk than multiple voltage approaches.
In addition, it would also be desirable to arrive at some way of providing a TCAM cell with two data storage cells that provides greater flexibility in the placement and/or pitch of compare data lines.